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vmmk-2303 0.5 to 6 ghz 1.8 v e-phemt shutdown lna in wafer level package data sheet description avagos vmmk-2303 is an easy-to-use gaas mmic amplifer that ofers excellent noise fgure and fat gain from 0.5 to 6 ghz in a miniaturized wafer level package (wlp). it operates from 1.8v cmos supply or 3.3v battery supply. the bias circuit has incorporated a power down feature which is accessed from the input port. the input and output are matched to 50 (better than 2:1 swr) across the entire bandwidth; no external matching is needed. this amplifer is fabricated with enhancement e-phemt technology and industry leading revolutionary wafer level package. the wafer level package is small and ultra thin yet can be handled and placed with standard 0402 pick and place assembly. wlp 0402, 1mm x 0.5mm x 0.25 mm attention: observe precautions for handling electrostatic sensitive devices. esd machine model = 50v esd human body model = 125v refer to avago application note a004r: electrostatic discharge, damage and control. pin connections (top view) note: e = device code y = month code features ? 1 x 0.5 mm surface mount package ? ultrathin (0.25mm) ? power down function ? 1.8v supply ? 50ohm input and output match ? rohs6 + halogen free specifcations (3ghz, 1.8v, 21ma typ.) ? noise figure: 2.0db typical ? associated gain: 14db ? output ip3: +22dbm ? output p1db: +9dbm applications ? low noise and driver for cellular/pcs and wcdma base stations ? 2.4 ghz, 3.5ghz, 5-6ghz wlan and wimax notebook computer, access point and mobile wireless applications ? 802.16 & 802.20 bwa systems ? wll and mmds transceivers ? radar, radio and ecm systems ey ey output / vdd input / vc amp input / vc output / vdd
2 table 1. absolute maximum ratings [1] sym parameters/condition unit absolute max vd supply voltage (rf output) [2] v 5 vc power down control voltage v 3 id device current [2] ma 60 p in, max cw rf input power (rf input) [3] dbm +13 p diss total power dissipation mw 300 tch max channel temperature c 150 jc thermal resistance [4] c/w 140 notes 1. operation in excess of any of these conditions may result in permanent damage to this device. 2. bias is assumed dc quiescent conditions 3. with the dc (typical bias) and rf applied to the device at board temperature tb = 25c 4. thermal resistance is measured from junction to board using ir method table 2. dc and rf specifcations t a = 25c, frequency = 3 ghz, vd = 1.8v, vc = 1.8v, z in = z out = 50 (unless otherwise specifed) sym parameters/condition unit minimum typ. maximum id device current ma 15 21 28 id_leakage current in shut down mode a 0.03 20 nf [1] noise figure db C 2 2.6 ga [1] associated gain db 12 14 16 oip3 [2,3] output 3rd order intercept dbm +22 C output p-1db [2] output power at 1db gain compression dbm +9 C irl [2] input return loss db C -13 C orl [2] output return loss db C -19 C notes: 1. measure data obtained using 300um g-s probe on production wafers 2. measure data obtained using 300um g-s-g probe on pcb substrate 3. oip3 test condition: f1=3.0ghz, f2=3.01ghz, pin=-20dbm
3 product consistency distribution charts at 3.0 ghz, vd = 1.8 v, vc = 1.8v id at vd=vc=1.8v, lsl=15ma, mean=21ma, usl=28ma id_of at vd=1.8v & vc=0v, mean=0.025ua, usl=20ua gain at 3ghz, lsl=12 db, mean=14 db, usl=16 db note: distribution data based on 500 part sample size from 3 lots during initial characterization. measurements were obtained using 300um g-s production wafer probe. future wafers allocated to this product may have nominal values anywhere between the upper and lower limits. nf at 3ghz, mean=2 db, usl=2.6 db .015 .017 .019 .021 .023 .025 .027 lsl lsl usl 12 12.5 13 13.5 15 14 14.5 16 15.5 usl 0.00002 0 .00001 .00002 lsl usl 1.4 1.6 1.8 2 2.2 2.6 2.4 usl
4 vmmk-2303 typical performance (t a = 25c, vdd = 1.8v, vc = 1.8v, idd = 21ma, z in = z out = 50 unless noted) figure 1. small-signal gain [1] figure 3. input return loss [1] figure 5. output p-1db [1] figure 2. noise figure [1] figure 4. output return loss [1] figure 6. output ip3 [1,2] notes: 1. data taken on a g-s-g probe substrate fully de-embedded to the reference plane of the package 2. output ip3 data taken at pin=-15dbm 0 5 10 15 20 0 1 2 3 4 5 6 7 frequency (ghz) s21 (db) frequency (ghz) s11 (db) 0 2 4 6 8 10 12 0 1 2 3 4 5 6 7 frequency (ghz) op1db (dbm) 0 1 2 3 0 1 2 3 4 5 6 7 frequency (ghz) nf (db) -25 -20 -15 -10 -5 0 0 1 2 3 4 5 6 7 frequency (ghz) s22 (db) 0 5 10 15 20 25 0 1 2 3 4 5 6 7 frequency (ghz) oip3 (dbm) -20 -15 -10 -5 0 0 1 2 3 4 5 6 7
5 vmmk-2303 typical performance (continue) (t a = 25c, vdd = 1.8v, vc = 1.8v, idd = 21ma, z in = z out = 50 unless noted) figure 7. total current over vdd [1] figure 9. gain over vdd [1] figure 11. input return loss over vdd [1] figure 8. noise figure over vdd [1] figure 10. isolation over vdd [1] figure 12. output return loss over vdd [1] notes: 1. data taken on a g-s-g probe substrate fully de-embedded to the reference plane of the package 0 10 20 30 0 1 2 3 4 vd (v) id (ma) 0 0.5 1 1.5 2 2.5 3 0 1 2 3 4 5 6 7 frequency (ghz) nf (db) vd=1.8v, vc=1.8v vd=3.3v, vc=1.8v 0 5 10 15 20 0 1 2 3 4 5 6 7 frequency (ghz) s21 (db) -20 -15 -10 -5 0 0 1 2 3 4 5 6 7 frequency (ghz) s11 (db) -30 -25 -20 -15 -10 -5 0 0 1 2 3 4 5 6 7 frequency (ghz) s12 (db) -25 -20 -15 -10 -5 0 0 1 2 3 4 5 6 7 frequency (ghz) s22 (db) vd=1.8v, vc=1.8v vd=3.3v, vc=1.8v vd=1.8v, vc=1.8v vd=3.3v, vc=1.8v vd=1.8v, vc=1.8v vd=3.3v, vc=1.8v vd=1.8v, vc=1.8v vd=3.3v, vc=1.8v
6 vmmk-2303 typical performance (continue) (t a = 25c, vdd = 1.8v, vc = 1.8v, idd = 21ma, z in = z out = 50 unless noted) figure 13. output p-1db over vdd [1] figure 15. gain over temp [3] figure 17. p1db over temp [3] figure 14. output ip3 over vdd [1,2] figure 16. noise figure over temp [3] figure 18. output ip3 over temp [2,3] notes: 1. data taken on a g-s-g probe substrate fully de-embedded to the reference plane of the package 2. output ip3 data taken at pin=-15dbm 3. over temp data taken on a test fxture (figure 20) without de-embedding 0 2 4 6 8 10 12 14 0 1 2 3 4 5 6 7 frequency (ghz) op1db (dbm) 0 5 10 15 20 0 1 2 3 4 5 6 7 frequency (ghz) s21 (db) 25c 85c -40c 0 3 6 9 12 15 0 1 2 3 4 5 6 7 frequency (ghz) p1db (dbm) 0 5 10 15 20 25 30 0 1 2 3 4 5 6 7 frequency (ghz) oip3 (dbm) 0 5 10 15 20 25 30 0 1 2 3 4 5 6 7 frequency (ghz) oip3 (dbm) vd=1.8v, vc=1.8v vd=3.3v, vc=1.8v vd=1.8v, vc=1.8v vd=3.3v, vc=1.8v 25c 85c -40c 25c 85c -40c 0 0.5 1 1.5 2 2.5 3 0 1 2 3 4 5 6 7 frequency (ghz) nf (db) 25c 85c -40c
7 vmmk-2303 typical s-parameters (data obtained using 300um g-s-g pcb substrate, losses calibrated out to the package reference plane; t a = 25c, vdd = 1.8v, vc = 1.8v, idd = 21ma, z in = z out = 50 unless noted) freq ghz s11 s21 s12 s22 db mag phase db mag phase db mag phase db mag phase 0.1 -1.189 0.872 -25.218 13.588 4.780 -178.071 -25.597 0.053 59.673 -28.754 0.037 102.740 0.2 -3.285 0.685 -40.252 14.034 5.032 178.844 -21.873 0.081 39.048 -24.013 0.063 56.683 0.3 -5.171 0.551 -48.030 14.274 5.173 175.178 -20.621 0.093 25.793 -22.476 0.075 36.971 0.4 -6.965 0.449 -48.479 14.334 5.209 174.141 -20.114 0.099 20.372 -20.819 0.091 43.571 0.5 -8.033 0.397 -49.998 14.383 5.238 171.490 -19.862 0.102 14.988 -20.734 0.092 34.642 0.9 -10.340 0.304 -55.088 14.389 5.241 161.829 -19.502 0.106 2.738 -20.602 0.093 17.406 1 -10.633 0.294 -56.660 14.355 5.221 159.550 -19.469 0.106 0.569 -20.327 0.096 14.799 1.5 -11.604 0.263 -66.322 14.237 5.151 148.646 -19.510 0.106 -7.764 -20.247 0.097 5.593 2 -12.465 0.238 -77.367 14.066 5.050 138.043 -19.609 0.105 -14.262 -20.455 0.095 -4.429 2.5 -13.120 0.221 -92.069 13.921 4.967 127.967 -19.777 0.103 -20.126 -19.854 0.102 -10.667 3 -13.756 0.205 -105.553 13.761 4.876 117.996 -20.044 0.100 -25.917 -19.315 0.108 -16.656 3.5 -14.080 0.198 -121.275 13.625 4.800 108.216 -20.355 0.096 -31.482 -18.577 0.118 -19.883 4 -14.164 0.196 -138.080 13.528 4.747 98.536 -20.819 0.091 -36.539 -17.215 0.138 -24.628 4.5 -14.080 0.198 -155.711 13.469 4.715 88.588 -21.473 0.084 -41.043 -15.682 0.164 -28.934 6 -10.734 0.291 137.934 13.064 4.500 53.142 -22.639 0.074 -39.719 -11.962 0.252 -67.155 6.5 -9.789 0.324 112.577 12.421 4.179 41.188 -21.971 0.080 -42.502 -12.385 0.240 -84.103 7 -9.114 0.350 90.524 11.686 3.840 30.984 -21.598 0.083 -49.096 -13.416 0.213 -97.269 7.5 -8.552 0.374 71.896 11.011 3.553 21.893 -21.639 0.083 -56.813 -14.572 0.187 -106.937 8 -7.985 0.399 55.866 10.407 3.314 13.237 -21.927 0.080 -64.022 -15.783 0.163 -114.375 8.5 -7.414 0.426 41.571 9.855 3.110 4.832 -22.395 0.076 -71.213 -16.936 0.142 -119.103 9 -6.934 0.450 28.414 9.336 2.930 -3.596 -22.987 0.071 -78.204 -18.048 0.125 -123.159 9.5 -6.519 0.472 16.304 8.820 2.761 -12.097 -23.702 0.065 -85.057 -19.188 0.110 -125.957 10 -6.152 0.493 5.143 8.292 2.598 -20.481 -24.539 0.059 -92.301 -20.175 0.098 -128.274 10.5 -5.857 0.510 -5.889 7.753 2.442 -28.823 -25.449 0.053 -98.980 -21.412 0.085 -129.273 11 -5.698 0.519 -16.421 7.207 2.293 -37.155 -26.558 0.047 -106.295 -22.418 0.076 -129.884 11.5 -5.647 0.522 -26.546 6.634 2.146 -45.392 -27.894 0.040 -114.058 -23.504 0.067 -129.694 12 -5.668 0.521 -36.450 6.034 2.003 -53.627 -29.499 0.034 -122.428 -24.657 0.059 -128.305 12.5 -5.769 0.515 -46.265 5.403 1.863 -61.689 -31.437 0.027 -131.444 -25.900 0.051 -125.420 13 -6.024 0.500 -56.018 4.750 1.728 -69.652 -33.893 0.020 -143.164 -26.859 0.045 -119.561 13.5 -6.384 0.480 -65.570 4.058 1.596 -77.410 -36.954 0.014 -157.876 -27.597 0.042 -113.832 14 -6.786 0.458 -74.640 3.346 1.470 -84.974 -40.537 0.009 176.577 -28.382 0.038 -107.341
8 figure 19. example application of vmmk-2303 at 3ghz figure 20. evaluation/test board (available to qualifed customer request) vmmk-2303 application and usage (please always refer to the latest application note an5378 in website) biasing and operation the vmmk-2303 can be used as a low noise amplifer or as a driver amplifer. the nominal bias condition for the vmmk-2303 is vd=vc=1.8v. at this bias condition the vmmk-2303 provides an optimal compromise between power consumption, noise fgure, gain, power output and oip3. the vmmk-2303 can also be operated a vd of 3.3v and a vc of 1.8v which will result in higher p1db and oip3. amp input vc vdd output size: 1.1 mm x 0.6 mm (0402 component) 50 ohm line 50 ohm line 10 k 100 pf 0.1 uf 15 nh 100 pf output pad ground pad input pad 100 pf at vc=1.8v, the corresponding drain currents are approxi - mately 21 and 23 ma at vd of 1.8v and 3.3v respectively. the vmmk-2303 is biased with a positive supply connected to the output pin through an external user supplied bias- tee as shown in figure 19. the power down feature (vc) at the input port is accessed through an external 10k? resistor. the resistor will have minimal efect on circuit performance. the lna is turned on when vc is at 1.8v and shut of when vc is at 0v. in a typical application, the bias- tee on the output port can be constructed using lumped elements. the value of the output inductor can have a major efect on both low and high frequency operation. the demo board uses a 15 nh inductor that has self resonant frequency higher than the maximum desired frequency of operation. if the self-resonant frequency of the inductor is too close to the operating band, the value of the inductor needs to be adjusted so that the self- resonant frequency is signifcantly higher than the highest frequency of operation. extending the low frequency response of the vmmk-2303 is possible by using two diferent value inductors in series with the smaller value inductor placed closest to the device and favoring the higher frequencies. the larger value inductor will then ofer better low frequency performance by not loading the output of the device. the parallel combination of the 100pf and 0.1uf capacitors provide a low impedance in the band of operation and at lower frequencies and should be placed as close as possible to the inductor. the low frequency bypass provides good rejection of power supply noise and also provides a low impedance termi - nation for third order low frequency mixing products that will be generated when multiple in-band signals are injected into any amplifer. it is also suggested that a 0.1uf capacitor be used to bypass the 10k resistor that feeds the vc terminal. this will prevent noise and other spurious from afecting the noise fgure of the vmmk-2303. refer the absolute maximum ratings table for allowed dc and thermal conditions. s parameter measurements the s-parameters are measured on a .016 inch thick ro4003 printed circuit test board, using g-s-g (ground signal ground) probes. coplanar waveguide is used to provide a smooth transition from the probes to the device under test. the presence of the ground plane on top of the test board results in excellent grounding at the device under test. a combination of solt (short - open - load - thru) and trl (thru - refect - line) calibration tech - niques are used to correct for the efects of the test board, resulting in accurate device s-parameters. the reference plane for the s parameters is at the edge of the package. the product consistency distribution charts shown on page 2 represent data taken by the production wafer probe station using a 300um g-s wafer probe. the ground-signal probing that is used in production allows the device to be probed directly at the device with minimal common lead inductance to ground. therefore there will be a slight dif - ference in the nominal gain obtained at the test frequency using the 300um g-s wafer probe versus the 300um g-s-g printed circuit board substrate method.
9 recommended smt attachment the vmmk packaged devices are compatible with high volume surface mount pcb assembly processes. manual assembly for prototypes 1. follow esd precautions while handling packages. 2. handling should be along the edges with tweezers or from topside if using a vacuum collet. 3. recommended attachment is solder paste. please see recommended solder refow profle. conductive epoxy is not recommended. hand soldering is not recommended. 4. apply solder paste using either a stencil printer or dot placement. the volume of solder paste will be dependent on pcb and component layout and should be controlled to ensure consistent mechanical and electrical performance. excessive solder will degrade rf performance. 5. follow solder paste and vendors recommendations when developing a solder refow profle. a standard profle will have a steady ramp up from room tempe- rature to the pre-heat temp to avoid damage due to thermal shock. 6. packages have been qualifed to withstand a peak temperature of 260 c for 20 to 40 sec. verify that the profle will not expose device beyond these limits. 7. clean of fux per vendors recommendations. 8. clean the module with acetone. rinse with alcohol. allow the module to dry before testing. outline drawing notes: 1. ? indicates pin 1 2. dimensions are in millimeters 3. pad material is minimum 5.0 um thick au suggested pcb material and land pattern notes: 1. 0.010 rogers ro4350 ey 0.25mm 0.5 mm 1.00mm 0 . 2 m m 0 . 3 m m 0 . 7 m m 0. 8mm 0 . 5 m m top view side view bottom view 3 figure 5. recommended pcb layout for vmmk devices 1.2 (0.048) 0.100 (0.004) 0.500 (0.020) 0.500 (0.020) 0.400 (0.016) 0.100 (0.004) 0.254 dia pth (0.010) 4pl 0.400 dia (0.016) 4pl 0.200 (0.008) 0.381 (0.015) 2pl 0.200 (0.008) part of input circuit part of output circuit 0.076 max (0.003) 2pl - see discussion solder mask 0.7 (0.028) printed circuit board material and vias the pcb board material stack used to qualify the device consists of 40 mil thickness fr4 core material with one ounce copper for both top and bottom metal. soldering onto materials with greater thermal expansion than fr5 or high tg fr4 should be avoided. board materials with high cte, such as tefon, may lead to damage of the base of the gaas package which contains the device circuitry or may lead to damage of the cap of the gaas package which defnes the air cavity, or may lead to damaging both. low loss microwave materials such as ro4003 and ro4350 have ctes similar to fr4 type material and should be acceptable pcb materials. recommended pcb foot p rint and grounding establishing a proper ground for either the source leads of the vmmk-1xxx series or the common leads of the vmmk-2xxx and -3xxx series is paramount. the rec- ommended printed circuit board via pattern is shown in figure 5. this is a non-solder mask defned footprint (nsmd). the outline of the solder mask that borders the device is shown by the area indicated in green. the recommended footprint does not require any plated through holes under the device. modeling and tests indicate that placing vias adjacent to (within .003) and on either side of the device as shown in figure 5 provides good grounding for the vmmk-2xxx and vmmk-3xxx series devices when mounted on .010 thickness ro4350 printed circuit board material. this technique also applies when using the vmmk-1xxx discrete fets at frequencies greater than 10 ghz. when using the vmmk-1xxx fets at low frequencies, some amount of source inductance may actually be required. in this case, the vias may be placed further away from the device to enhance stability. consult individual application notes for more information. due to the proximity of the vias to the edge of the vmmk device (less than .003 ), it is recommended that the vias be flled to minimize wicking of the solder from under the vmmk device. in addition, since the edge of the vias is slightly outside of the solder mask area, the vias should be flled. vias can be flled with a conductive via fll material or a non-conductive via fll material. possible non-conductive via fll materials include: san-ei kagaku php-900 ir6 taiyo ink hb 12000 db4 dielectric prepreg material solder mask material as a general rule, if a via is within .004 (100u) of the edge of the soldermask but not under the device, then the via should be flled. any via which is covered by the solder mask and is beyond .004 (100u) of the solder mask edge can be uncapped and unflled as it is not at risk of wicking away solder from the device. if for any reason it is required to include a via or vias under a vmmk device, then the vias should be flled and capped. a capped via is a plated over flled via. if a flled but uncapped via is placed under the device, there will not be enough solderable surface area for device attach- ment. if an unflled and uncapped via is placed directly under the ground pad, then the liquid solder will fow into the open via hole during the refow process and deplete the solder volume to varying degrees from under the ground pad. depletion of the solder volume due to unflled vias may lead to a weak solder joint, poor grounding of the device, and/or stresses compromising the structural integrity of the package. the recommended footprint provides a solder joint that meets jedec standards for die shear, and provides sufcient adhesion of the ground lead such that the mechanical integrity of the package remains intact should any minor deformation of the board occur due to thermal shock.
10 ordering information part number devices per container container vmmk-2303-blkg 100 antistatic bag VMMK-2303-TR1G 5000 7 reel package dimension outline reel orientation device orientation top view end view ? ey ? ey ? ey ? ey 8 mm 4 mm note: ?c? = device code ?y? = month code u s e r f e e d d i r e c ti o n not e: all dimensions ar e in mm a e d d ie dimension: d im range unit d 1.004 - 1.085 mm e 0.500 - 0.585 mm a 0.225 - 0.275 mm user feed direction carrier tape reel
for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2012 avago technologies. all rights reserved. av02-2002en - december 26, 2012 notice: 1. 10 sprocket hole pitch cumulative tolerance is 0.1mm. 2. pocket position relative to sprocket hole measured as true position of pocket not pocket hole. 3. ao & bo measured on a place 0.3mm above the bottom of the pocket to top surface of the carrier. 4. ko measured from a plane on the inside bottom of the pocket to the top surface of the carrier. 5. carrier camber shall be not than 1m per 100mm through a length of 250mm. unit: mm symbol spec. k1 C po 4.00.10 p1 4.00.10 p2 2.00.05 do 1.550.05 d1 0.50.05 e 1.750.10 f 3.500.05 10po 40.00.10 w 8.00.20 t 0.200.02 note: 2 p2 note: 1 po do b b note: 2 e f w a a p1 d1 r0.1 ao 5 (max) scale 5:1 aa section ao = 0.730.05 mm bo = 1.260.05 mm ko = 0.35 +0.05 mm +0 scale 5:1 bb section 5 (max) bo ko t tape dimensions

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